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silego technology, inc. rev 1.01 000-0059h1017-101 revised november 2, 2017 SLG59H1017V a 13.3 m ? , 4 a, integrated power sw itch with 12v/24v input lockout select and analog current monitor output block diagram and 3 a typical application circuit general description the SLG59H1017V is a high-performance 13.3 m ? nmos power switch designed to control 12 v or 24 v power rails up to 4 a. using a proprietary mosfet design, the SLG59H1017V achieves a stable 13.3 m ? rds on across a wide input voltage range. in combining novel fet design and copper pillar interconnects, the SLG59H1017V package also exhibits a low thermal resistance for high-current operation. designed to operate over a -40 c to 85 c range, the SLG59H1017V is available in a low thermal resistance, rohs-compliant, 1.6 x 3.0 mm stqfn package. features ? wide operating input voltage: 12 v or 24 v ? maximum continuous switch current: 4 a ? automatic nfet soa protection ? high-performance mosfet switch low rds on : 13.3 m ? at v in = 24 v low ? rds on / ? v in : <0 .05 m ? /v low ? rds on / ? t: < 0 . 0 6 m ? /c ? pin-selectable 12v/24v input overvoltage and undervoltage lockout ? capacitor-adjustable inrush current control ? two stage current limit protection: resistor-adjustable active current limit internal short-circuit current limit ? open drain fault signaling ? analog mosfet current monitor output: 10 a/a ?fast 4 k ? output discharge ? pb-free / halogen-free / rohs compliant packaging pin configuration applications ? power-rail switching ? multifunction printers ? large-format copiers ? telecommunications equipment ? high-performance computing 12 v and 24 v point-of-load power distribution ? motor drives on 1 fault cap gnd gnd 2 3 15 16 vin 4 vout sel 13 14 rset 18 iout vin vin 5 6 vin 7 vout 12 vout vout 10 11 17 vin vout 89 18-pin stqfn 1.6 x 3.0 mm, 0.40mm pitch (top view) SLG59H1017V on 3 v fs - connect to system adc connect to system gpi charge pump c slew 10 nf r pu 100 k linear ramp control state machine (cl/sc detection and over temperature protection) discharge cmos input 27 v ovlo 20.5 v uvlo r set 30.1 k ? c 1 47 f r iout 84.5 k ? gnd off 24 v v in lockout selected c 2 22 f c 3 0.1 f v logic c iout 180 pf r pu 10 k ? v logic c 5 47 f c 6 22 f c load = c 5 + c 6 sel fault vout on cap rset vin iout 24 v 5% 3a c in = c 1 + c 2 + c 3
000-0059h1017-101 page 2 of 34 SLG59H1017V pin description ordering information pin # pin name type pin description 1 on input a low-to-high transition on this pin initiate s the operation of t he SLG59H1017V?s state machine. on is an asserted high, level-sensitive cmos input with v il < 0.3 v and v ih > 0.9 v. as the on pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (gpo) of a microcontrolle r, an application processor, or a system controller ? do not allow this pi n to be open-circuited. 2 gnd gnd pin 2 is a low-current gnd terminal for the SLG59H1017V. connect directly to pin 3 3gnd gnd pin 3 is the main ground connection for the SLG59H1017V?s internal charge pump, its gate drive and current-limit circuits as well as its internal state machine. therefore, use a short, stout connection from pin 3 to the system?s analog or power plane. 4-8 vin mosfet vin supplies the power for the operation of the SLG59H1017V, its internal control circuitry, and the drain terminal of the nfet power switch . with 5 pins fused together at vin, connect a 47 f (or larger) low-esr capacitor from this pin to ground. capacitors used at vin should be rated at 50 v or higher. 9-13 vout mosfet source terminal of n-channel mosfet (5 pins fused for vout). connect a 47 f (or larger) low-esr capacitor from this pin to ground. ca pacitors used at vout should be rated at 50 v or higher. 14 sel input as a low logic-level cmos input with v il < 0.3 v and v ih > 1.65 v, sel selects one of two undervoltage/overvoltage lockout windows. when sel = low, the v in undervoltage/overvoltage lockout window is set for 12 v 10% applications. when sel = high, the v in undervoltage/overvoltage lockout window is set for 24 v 5% applications. see the electrical characte ristics table for additional information. 15 fault output an open drain output, fault is asserted within tfault low when a v in undervoltage, v in overvoltage, a current-limit, or an ove r-temperature condition is detected. fault is deasserted within tfault high when the fault condition is removed. connect a 100 k ? external resistor from the fault pin to local system logic supply. 16 cap output a low-esr, stable dielectric, ceramic surface-mount capacitor connected from cap pin to gnd sets the v out slew rate and overall turn-on ti me of the SLG59H1017V. for best performance, the range for c slew values are 10 nf c slew 20 nf ? please see typical characteristics for additional information. capa citors used at the cap pin should be rated at 10 v or higher. see equation for selecting capacitor and start-up slewing. 17 iout output iout is the SLG59H1017V?s power mosfet load current monitor output. as an analog output current, this signal when applied to a ground-reference resistor generates a voltage proportional to the current through the n-channel mosfet. the i out transfer characteristic is typically 10 a/a with a voltage compliance range of 0.5 v v iout 4 v. optimal i out linearity is exhibited for 0.5 a i ds 4 a. in addition, it is recommended to bypass the iout pin to gnd with a 0.18 nf capacitor. 18 rset input a 1%-tolerance, metal-film resistor between 20 k ? and 91 k ? sets the SLG59H1017V?s active current limit. a 91 k ? resistor sets the SLG59H1017V?s active current limit to 1 a and a 20 k ? resistor sets the active current limit to 4.5 a. part number type production flow SLG59H1017V stqfn 18l fc industrial, -40 c to 85 c SLG59H1017Vtr stqfn 18l fc (tape and reel) industrial, -40 c to 85 c
000-0059h1017-101 page 3 of 34 SLG59H1017V absolute maximum ratings parameter description conditions min. typ. max. unit v in to gnd power switch input voltage to gnd continuous -0.3 -- 30 v maximum pulsed v in , pulse width <0.1s -- -- 32 v v out to gnd power switch output voltage to gnd -0.3 -- v in v on, sel, cap, rset, iout, and fault to gnd on, sel, cap, rset, iout, and fault pin voltages to gnd -0.3 -- 7 v t s storage temperature -65 -- 150 c esd hbm esd protection human body model 2000 -- -- v esd cdm esd protection charged device model 500 -- -- v msl moisture sensitivity level 1 ja package thermal resistance, junction-to-ambient 1.6 x 3.0 mm 18l stqfn; de- termined with the device mount- ed onto a 1 in 2 , 1 oz. copper pad of fr-4 material -- 40 -- c/w mosfet ids cont continuous current from vin to vout t j < 150c -- -- 4 a mosfet ids peak peak current from vin to vout maximum pulsed switch current, pulse width < 1 ms -- -- 6 a note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a s tress rating only and functional operation of the device at these or any other conditions above thos e indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability. electrical characteristics 12 v v in 24 v; c in = 47 f, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c parameter description conditions min. typ. max. unit v in operating input voltage 10.8 -- 25.2 v v in(ovlo) v in overvoltage lockout threshold v in ; sel = high 25.3 27 28.5 v v in ; sel = low 13.3 13.7 14.5 v v in(uvlo) v in undervoltage lockout threshold v in ; sel = high 19.5 20.5 21.5 v v in ; sel = low 9.7 10.2 10.7 v i q quiescent supply current on = high; i ds = 0 a -- 0.5 0.6 ma i shdn off mode supply current on = low; i ds = 0 a -- 1 3 a rds on on resistance t a = 25c; i ds = 0.1 a -- 13.3 14 m ? t a = 85c; i ds = 0.1 a -- 16.8 19 m ? mosfet ids current from vi n to vout continuous -- -- 4 a i limit active current limit, i acl v out > 0.5 v; r set = 30.1 k ? 3.03.193.5 a short-circuit current limit, i scl v out < 0.5 v -- 0.5 - a t acl active current limit response time v in = 12 v; r set = 91 k ? ; c load = 10 f; switch in 10 ? load 117 150 220 s r dschrg output discharge resistance v out = 0.4 v input bias; on = low 3.5 4.4 5.3 k ? i out analog mosfet current monitor output i ds = 1 a 9.3 10 10.7 a i ds = 3 a 28.53031.5a
000-0059h1017-101 page 4 of 34 SLG59H1017V t iout i out response time to change cur- rent in main mosfet c iout = 180 pf; step load 0 to 2.4 a; 0% to 90% i out -- 45 -- s c load output load capacitance c load connected from vout to gnd -- 47 -- f t on_delay on delay time 50% on to 10% v out ; v in = 12 v; c slew = 10 nf; r load = 100 ? , c load = 10 f 480 600 720 s 50% on to 10% v out ; v in = 24 v; c slew = 10 nf; r load = 100 ? , c load = 10f 0.8 1.0 1.2 ms t to ta l _ o n total turn-on time 50% on to 90% v out set by external c slew 1 ms 50% on to 90% v out ; v in = 12 v; c slew = 10 nf; r load = 100 ? , c load = 10 f 2.9 3.6 4.3 ms 50% on to 90% v out ; v in = 24 v; c slew = 10 nf; r load = 100 ? , c load = 10 f 5.7 7.1 8.5 ms v out(sr) v out slew rate 10% v out to 90% v out set by external c slew 1 v/ms 10% v out to 90% v out ; v in = 12 v or 24 v; c slew = 10 nf; r load = 100 ? , c load = 10 f 2.7 3.2 3.9 v/ms t off_delay off delay time 50% on to v out ; r load = 100 ? , no c load -- 15 -- s t fall v out fall time 90% v out to 10% v out ; on = high-to-low; v in = 12 v or 24 v; r load = 100 ? , no c load 10.412.714.3 s tfault low fault assertion time abnormal step load current event to fault ; i acl = 1 a; v in = 24 v; r set = 91 k ? ; switch in 20 ? load -- 80 -- s tfault high fault de-assertion time delay to fault after fault condition is removed; i acl = 1 a; v in = 24 v; r set = 91 k ? ; switch out 20 ? load -- 180 -- s fault vol fault output low voltage i fault = 1 ma -- 0.2 -- v on_v ih on pin input high voltage 0.9 -- 5 v on_v il on pin input low voltage -0.3 0 0.3 v sel_v ih sel pin input high voltage 1.65 -- 4.5 v sel_v il sel pin input low voltage -0.3 -- 0.3 v i on(leakage) on pin leakage current 1 v on 5 v or on = gnd -- -- 1 a therm on thermal protection shutdown threshold -- 145 -- c therm off thermal protection restart threshold -- 125 -- c notes: 1. refer to typical timing parameter vs. c slew performance charts for additional information. electrical characteristics (continued) 12 v v in 24 v; c in = 47 f, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c parameter description conditions min. typ. max. unit
000-0059h1017-101 page 5 of 34 SLG59H1017V t on_delay , v out(sr) , and t total_on timing details 90% v out 50% on t on_delay v out(sr) (v/ms) on v out t to t a l _ o n 10% v out 50% on 10% v out t off_delay t fall 90% v out
000-0059h1017-101 page 6 of 34 SLG59H1017V typical performance characteristics rds on vs. temperature and v in i acl vs. temperature and r set
000-0059h1017-101 page 7 of 34 SLG59H1017V i acl vs. r set i out vs. mosfet ids and v in
000-0059h1017-101 page 8 of 34 SLG59H1017V i out vs. temperature and mosfet ids v out slew rate vs. temperature, v in , and c slew
000-0059h1017-101 page 9 of 34 SLG59H1017V t total_on vs. c slew and v in
000-0059h1017-101 page 10 of 34 SLG59H1017V timing diagram - basic operation including active current limit protection v in on time low high tfault high v out i ds 90% 10% t on_delay active current limit operation fault high i scl i acl i scl i acl on tfault low nominal steady state operation resumes acl threshold triggered abnormal step load current event t rise
000-0059h1017-101 page 11 of 34 SLG59H1017V timing diagram - active current limit & thermal protection operation v out i ds 90% 10% t on_delay active current limit operation thermal protection operation i scl i acl i scl i acl tfault high fault v in on time low high nominal steady state operation resumes tfault low die temp > therm on abnormal step load current event t rise t to ta l _ o n die temp < therm off
000-0059h1017-101 page 12 of 34 SLG59H1017V timing diagram - basic operation including active current + internal fet soa protection v in on time low high tfault high v out i ds 90% 10% 0.2s t on_delay active current limit operation fault high i scl i acl i scl i acl on tfault low acl threshold triggered nominal steady state operation resumes once overload condition is removed automatic restart after 0.2s ?cool off? delay and normal operation resumes if overload condition is removed fet soa threshold triggered and fet is turned off acl threshold triggered abnormal step load current event soa threshold t rise decreasing r load drops v out soa protection
000-0059h1017-101 page 13 of 34 SLG59H1017V SLG59H1017V application diagram typical turn-on waveforms figure 1. test setup application diagram figure 2. typical turn on operation waveform for v in = 12 v, c slew = 10 nf, c load = 10 f, r load = 100 ?
000-0059h1017-101 page 14 of 34 SLG59H1017V figure 3. typical turn on operation waveform for v in = 12 v, c slew = 18 nf, c load = 10 f, r load = 100 ? figure 4. typical turn on operation waveform for v in = 24 v, c slew = 10 nf, c load = 10 f, r load = 100 ?
000-0059h1017-101 page 15 of 34 SLG59H1017V typical turn-off waveforms figure 5. typical turn on operation waveform for v in = 24 v, c slew = 18 nf, c load = 10 f, r load = 100 ? figure 6. typical turn of f operation waveform for v in = 12 v, c slew = 10 nf, no c load , r load = 100 ?
000-0059h1017-101 page 16 of 34 SLG59H1017V figure 7. typical turn off operation waveform for v in = 12 v, c slew = 10 nf, c load = 10 f, r load = 100 ? figure 8. typical turn of f operation waveform for v in = 24 v, c slew = 10 nf, no c load , r load = 100 ?
000-0059h1017-101 page 17 of 34 SLG59H1017V typical acl operation waveforms figure 9. typical turn off operation waveform for v in = 24 v, c slew = 10 nf, c load = 10 f, r load = 100 ? figure 10. typical acl operation waveform for v in = 12 v, c load = 10 f, i acl = 1 a, r set = 91 k ?
000-0059h1017-101 page 18 of 34 SLG59H1017V figure 11. typical acl operation waveform for v in = 24 v, c load = 10 f, i acl = 1 a, r set = 91 k ? figure 12. thermally induced soa shutdown for v in = 24 v, c load = 10 f, r set = 91 k ? , i acl = 1 a, r load = 20 ? , acl operation results in high power dissipation the increasing temperature reduces the soa region. soa shutdown is triggered when the soa drops to the power dissipation level.
000-0059h1017-101 page 19 of 34 SLG59H1017V typical fault operation waveforms figure 13. typical fault assertion waveform for v in = 12 v, c load = 10 f, i acl = 1 a, r set = 91 k ? , switch on 9 ? load figure 14. typical fault de-assertion waveform for v in = 12 v, c load = 10 f, i acl = 1 a, r set = 91 k ? , switch out 9 ? load
000-0059h1017-101 page 20 of 34 SLG59H1017V figure 15. typical fault assertion waveform for v in = 24 v, c load = 10 f, i acl = 1 a, r set = 91 k ? , switch on 18.5 ? load figure 16. typical fault de-assertion waveform for v in = 24 v, c load = 10 f, i acl = 1 a, r set = 91 k ? , switch out 18.5 ? load
000-0059h1017-101 page 21 of 34 SLG59H1017V typical i out response time waveforms figure 17. typical i out response time waveform for v in = 12 v, c load = 10 f, r load = 12 ? c iout = 0.18 nf, r iout = 84.5 k ? , load step 0 a to 1 a figure 18. typical i out response time waveform for v in = 12 v, c load = 10 f, r load = 12 ? c iout = 0.18 nf, r iout = 84.5 k ? , load step 1 a to 0 a
000-0059h1017-101 page 22 of 34 SLG59H1017V figure 19. typical i out response time waveform for v in = 24 v, c load = 10 f, r load = 24 ? c iout = 0.18 nf, r iout = 84.5 k ? , load step 0 a to 1 a figure 20. typical i out response time waveform for v in = 24 v, c load = 10 f, r load = 24 ? c iout = 0.18 nf, r iout = 84.5 k ? , load step 1 a to 0 a
000-0059h1017-101 page 23 of 34 SLG59H1017V typical soa waveforms figure 21. typical soa waveform during power up on heavy load for v in = 12 v, c load = 10 f, r set = 30.1 k ? , r load = 3.5 ? figure 22. extended typical soa waveform during power up under heavy load for v in = 12 v, c load = 10 f, r set = 30.1 k ? , r load = 3.5 ?
000-0059h1017-101 page 24 of 34 SLG59H1017V figure 23. typical soa waveform during power up under heavy load for v in = 24 v, c load = 10 f, r set = 30.1 k ? , r load = 12 ? figure 24. extended typical soa waveform during power up under heavy load for v in = 24 v, c load = 10 f, r set = 30.1 k ? , r load = 12 ?
000-0059h1017-101 page 25 of 34 SLG59H1017V figure 25. typical non-monotonic v out ramping waveform duri ng power up on heavy load for v in = 24 v, c load = 470 f, r set = 91 k ? , r load = 40 ?
000-0059h1017-101 page 26 of 34 SLG59H1017V applications information hfet1 safe operating area explained silego?s hfet1 integrated power controllers incorporate a number of internal protection featur es that prevents them from damaging themselves or any other circuit or subcircuit downstr eam of them. one particular protection feature is their safe operation area (soa) protection. soa pr otection is automatically activated under overpower and, in some cases, under overcurrent conditions. overpower soa is activated if package power dissipation exceeds an internal 15 w threshold and hfet1 devices will quickly switch off (open circuit) upon overpower de tection and automatically resume (close) nominal operation once overpower condition no longer exists. one of the possible ways to have an overpower condition trigger soa protection is when hfet1 products are enabled into heavy output resistive loads and/or into large load capacitors. it is under these conditions to follow carefully the ?safe start-up l oading? guidance in the applications section of the datasheet. during an overcurrent condition, hfet1 devices will try to limit the out put current to the level set by the external r set resistor. limiting the output current, however, causes an increased voltage drop across the fet?s channel because the fet?s rds on increased as well. since the fet?s rds on is larger, package power dissipation also increases. if the resultant increase in package power dissipation is greater than or equal to 15 w, internal s oa protection will be triggered and the fet will open circuit (switch off). every time so a protection is triggered, all hfet1 devi ces will automatically attempt to resume nominal operation after 160 ms. the automatic retry attemp t only allows power-up with soa at 5 w. this soa fold back power ensures that the fet survives a short circuit condition. to clear the 5 w soa fold back, switc h the on pin to ?low? to power reset soa to 15 w. safe start-up condition SLG59H1017V has built-in protection to prevent over-heating during start-up into a heavy load. overloading the vout pin with a capacitor and a resistor may result in non-monotonic v out ramping ( figure 25 ) or repeated restarts ( figure 21 to figure 24 ). in general, under light loading on vout, v out ramping can be controlled with c slew value. the following equation serves as a guide: where t rise = total rise time from 10% v out to 90% v out v in = input voltage c slew = capacitor value for cap pin when capacitor and resistor loading on vout duri ng start up, the following tables will ensure v out ramping is monotonic without triggering internal protection: safe start-up loading for v in = 24 v (monotonic ramp) slew rate (v/ms) c slew (nf) 2 c load (f) r load ( ? ) 0.5 66.7 500 30 1.0 33.3 250 30 1.5 22.2 160 30 2.0 16.7 120 30 2.5 13.3 100 30 c slew = t rise v in x 4.9 a x 20 3
000-0059h1017-101 page 27 of 34 SLG59H1017V note 2: select the closest value tolerance capacitor. setting the SLG59H1017V?s active current limit note 3: active current limit accuracy is 15% over voltage range and over temperature range. configuring the SLG59H1017V for 12 v v in lockout applications to configure the SLG59H1017V for conditioned 12 v 10% v in applications is simply a matter of connecting the sel pin to gnd as shown in figure a . for other v in lockout window applications, please consult silego for additional information. safe start-up loading for v in = 12 v (monotonic ramp) slew rate (v/ms) c slew (nf) 2 c load (f) r load ( ? ) 1 33.3 500 8 2 16.7 250 8 3 11.1 160 8 4 8.3 120 8 5 6.7 100 8 r set (k ? ) active current limit (a) 3 91 1 45 2 30 3 20 4.5 on charge pump linear ramp control state machine (cl/sc detection and over temperature protection) discharge cmos input 13.7v ovlo 10.2v uvlo gnd off 12 v v in lockout selected figure a. 3 v fs - connect to system adc v logic c 5 47 f c 6 22 f c load = c 5 + c 6 vout connect to system gpi r pu 100 k r iout 84.5 k ? c iout 180 pf fault iout c slew 10 nf r set 30.1 k ? sel on cap rset 12 v 10% 3a c 1 47 f c 2 22 f c 3 0.1 f vin c in = c 1 + c 2 + c 3
000-0059h1017-101 page 28 of 34 SLG59H1017V 24 v v in and 12 v v in lockout window thresholds shown in figure b and figure c are the two sets of v in overvoltage/undervoltage lockout windows ? one for conditioned 24 v 5% v in systems and the second for conditioned 12 v 10% v in systems. to avoid lockout threshold collis ion with nominal operation, the SLG59H1017V?s v in(ovlo) min and v in(uvlo) max thresholds were set 0.1 v correspondingly higher than the system?s nominal v in max or lower than the system?s v in min range. power dissipation the junction temperature of the slg59h1 017v depends on different factors such as board layout, ambient temperature, and other environmental factors. the primary cont ributor to the increase in the junction temperature of the SLG59H1017V is the powe r dissipation of its power mosfet. its power dissipation and the ju nction temperature in nominal operating mode can be calculated using the following equations: where: pd = power dissipation, in watts (w) rds on = power mosfet on re sistance, in ohms ( ? ) i ds = output current, in amps (a) and where: t j = junction temperature, in celsius degrees (c) ja = package thermal resistance, in celsius degrees per watt (c/w) t a = ambient temperature, in celsius degrees (c) figure b. figure c. pd = rds on x i ds 2 t j = pd x ja + t a
000-0059h1017-101 page 29 of 34 SLG59H1017V power dissipation (continued) in current-limit mode, the SLG59H1017V?s power dissipation can be calculated by taking into account the voltage drop across the power switch (v in - v out ) and the magnitude of the output current in current-limit mode (i acl ): where: pd = power dissipation, in watts (w) v in = input voltage, in volts (v) r load = load resistance, in ohms ( ? ) i acl = output limited current, in amps (a) v out = r load x i acl pd = (v in -v out ) x i acl or pd = (v in ? (r load x i acl )) x i acl
000-0059h1017-101 page 30 of 34 SLG59H1017V package top marking system definition 1017v part code pin 1 identifier wwnnn date code + lot code arr assembly + rev. code 1017v - part id field ww - date code field 1 nnn - lot traceabi lity code field 1 a - assembly site code field 2 rr - part revision code field 2 note 1: each character in code field can be alphanumeric a-z and 0-9 note 2: character in code field can be alphabetic a-z
000-0059h1017-101 page 31 of 34 SLG59H1017V package drawing and dimensions 18 lead tqfn package 1.6 x 3 mm (fused lead) jedec mo-220, variation wcee
000-0059h1017-101 page 32 of 34 SLG59H1017V SLG59H1017V 18-pin stqfn pcb landing pattern note: all dimensions s hown in micrometers ( m)
000-0059h1017-101 page 33 of 34 SLG59H1017V tape and reel specifications carrier tape drawing and dimensions recommended reflow soldering profile please see ipc/jedec j-std-020: late st revision for reflow profile based on package volume of 2.64 mm 3 (nominal). more information can be found at www.jedec.org. package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 18l 0.4p fc green 18 1.6 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w stqfn 18l 0.4p fc green 1.78 3.18 0.76 4 4 1.5 1.75 3.5 8 refer to eia-481 specification
000-0059h1017-101 page 34 of 34 SLG59H1017V revision history date version change 11/2/2017 1.01 updated v in max and v in(ovlo) min fixed typos and formatting 3/28/2017 1.00 production release

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